A processor, executing a pipe-line control operation includes a branch prediction mechanism for making a prediction about an instruction branch to efficiently read instruction sequences, that is, an instruction fetch, from a memory to an instruction execution unit. Since the instruction fetch may be performed prior to execution of an instruction, the branch prediction mechanism is of great importance, especially in processors that perform out-of-order control.
In an instruction execution processing device proposed in the past, an entry of a branch history is related to an instruction address and the entry is formed by the number of blocks defined by the length of an instruction to be fetched and the minimum unit length of an instruction word.
[Patent Document 1] Japanese Laid-Open Patent Application 06-089173
[Patent Document 2] Japanese Laid-Open Patent Application 2004-38337
A reduction in power consumption, consumed during branch prediction processing, as much as possible is desirable for the branch prediction mechanism.